Various abbreviations that appear in the specification and/or in the drawing figures are defined as follows:
3GPP third generation partnership project
BSS base station subsystem
CN core network
CRNC controlling RNC
DBSS drift BSS
DL downlink
DPC downlink power control
DPCH dedicated physical channel
DRNC drift RNC
DRNS drift RNS
DSCH downlink shared channel
FDD frequency division duplex
F-DPCH fractional DPCH
IE information element
Iub interface between the RNC and a Node B
Iur logical interface between two RNC
Node B base station
P-CCPCH primary common control physical channel
P-CPICH primary common pilot channel
RAN radio access network
RL radio link
RLC radio link control
RNC radio network controller
RNS radio network subsystem
RNSAP radio network subsystem application part
RRC radio resource control
SAS stand-alone serving mobile location centre
SBSS serving BSS
S-CCPCH secondary common control physical channel
SCH synchronisation channel
SHO soft handover
SRNC serving RNC
SRNS serving RNS
TDD time division duplex
TPC transmit power control
TS time slot
UE user equipment
UL uplink
UMTS universal mobile telecommunications system
UTRA universal terrestrial radio access
UTRAN universal terrestrial radio access network
WCDMA wideband code division multiple access
In 3GPP Rel-7 (release 7) it was agreed to introduce a change to the Rel-6 (release 6) Fractional DPCH. The DPCH is a DL channel in which at most 10 UEs can time-share one DL channelization code for power control command delivery. The change involved removing a SHO timing restriction that was present in Rel-6. The enhancement was made so that the DL slot format of the F-DPCH may be chosen to be one of ten, which places the TPC symbol to one of the ten symbol positions in the DL slot.
Reference in this regard can be made to R1-070809, 3GPP TSG-RAN WG1 #48, St. Louis, USA, 12th-16th Feb., 2007, Change Request 25.211 CR232, rev. 2, Qualcomm Europe, attached to the above-referenced priority document as Exhibit A. The introduction of new slot formats was to allow the placement of the TPC symbol anywhere in the DL F-DPCH slot. The motivation for making this change was presented in R1-070811, 3GPP TSG-RAN WG1 #48, St. Louis, USA, 12th-16th Feb., 2007, “Benefits of DL code utilization with enhanced F-DPCH” Qualcomm Europe, attached to the above-referenced priority document as Exhibit B.
FIGS. 1C and 1D herein reproduce FIGS. 12B, Frame Structure for F-DPCH, and Table 16C, F-DPCH Fields, respectively, of R1-070809, and show that the TPC symbol (2 TPC bits) can assume any of the 10 symbol positions in a slot (as defined by slot format #0-#9).
In the SHO case each radio link may obtain a different F-DPCH slot format and thus different TPC symbol timing in the DL. However, due to power control timing it would be beneficial if the TPC symbol timing in all the radio links being received by a single UE would be similar, since if the timing difference is large the power control loop can experience a longer delay.
Further reference in this regard can be made to R1-070416, 3GPP TSG-RAN WG1 #47 bis, Sorrento, Italy, Jan. 15th-19th, 2007, “UL system analysis with proposed new F-DPCH” Qualcomm Europe, attached to the above-referenced priority document as Exhibit C. This publication describes why a large time difference in the TPC commands received by the UE in SHO from two different radio links leads to a two slot power control delay, while a smaller time difference leads to only a one slot power control delay.
It has been assumed that the CRNC determines the F-DPCH slot format for each RL established for the UE since it is the CRNC that allocates the channelization code used for the channel. Since the slot format is related to the channelization code, it may be assumed that the F-DPCH slot format is also changed when the code allocated to the F-DPCH is changed.
However, the inventors have realized that as currently specified it is not possible to change the F-DPCH slot format for the UE over the Iur by the DRNC, since in the Rel-6 specification there was only one slot format allowed for the F-DPCH, and furthermore the timing of multiple radio links was required to be within +/−148 chips from one another (approximately one tenth of a symbol time). Additionally, when adding a new radio link there is no mechanism specified that would facilitate attempting to allocate the DL F-DPCH timing of the RL being added so as to be close to the existing RL timings.